Publications

2011   2010   2009   2008   2007   2006   2005   2004   2003   2002   2001   2000   1999   1998   1997  

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    2011

    Journals:

  1. Vinay Saripalli, Guangyu Sun, Asit Mishra, Yuan Xie, Suman Datta and Vijaykrishnan Narayanan, "Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors," IEEE Journal on Emerging and Selected Topics in Circuits and Systems," , (in press) 2011. [PDF]
  2. E.Hwang, S.Mookerjea, M.K Hudait, S.Datta, "Investigation of scalability of In0.7Ga0.3As quantum well ?eld effect transistor (QWFET) architecture for logic applications," Solid-State Electronics, (in press) 2011. [PDF]
  3. D. Mohata, S. Mookerjea, A. Agrawal, Y. Li, T. Mayer, V. narayanan, A. Liu and S. Datta, "Experimental Staggered-Source and N+ Pocket-Doped Channel III-V Tunnel Field-Effect Transistors and Their Scalabilities," Applied Physics Express, vol 4, pp. 024105, February 2011. [PDF]
  4. A. Ali, B. Bennett, B. Boos, H. Madan, A. Agrawal, P. Schiffer, R. Misra and S. Datta, , "Experimental Determination of Quantum and Centroid Capacitance in Arsenide-Antimonide Quantum-Well MOSFETs Incorporating Non-Parabolicity Effect," accepted for publication in IEEE Transactions on Electron Devices , vol. ? , pp. ? , January 2011. [PDF]

    5. Conferences:

  5. V. Saripalli, J. P. Kulkarni, N. Vijaykrishnan and S. Datta, "Variation-Tolerant Ultra Low- Power Heterojunction Tunnel FET SRAM Design", accepted in IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), San Diego, CA, June 2011[PDF]
  6. A. Agrawal, A. Ali, R. Misra, P. E. Schiffer, J. B. Boos, B. R. Bennett and S. Datta, "Low Field Electron Transport in Mixed Arsenide Antimonide Quantum Well Heterostructures", accepted for publication in Electronic Materials Conference (EMC), Univ. of California, Santa Barbara, June 2011 [PDF]
  7. A. Agrawal, A. Ali, R. Misra, P. E. Schiffer, B. R. Bennett, J. B. Boos and S. Datta, "Experimental Determination of Dominant Scattering Mechanisms in Scaled InAsSb Quantum Well", accepted for publication in Device Research Conference (DRC), Univ. of California, Santa Barbara, June 2011 [PDF]
  8. R.Bijesh, I. OK, M. Baykan, C. Hobbs, P.Majhi, R.Jammy and S.Datta, "Hole Mobility Enhancement in Uniaxially Strained SiGe FINFETs: Analysis and Prospects", accepted for publication in Device Research Conference (DRC), Univ. of California, Santa Barbara, June 2011 [PDF]
  9. D. K. Mohata, R.Bijesh, V.Saripalli, T. Mayer and S.Datta, “ Self-aligned Gate NanoPillar In0.53Ga0.47As Vertical Tunnel Transistor", accepted for publication in Device Research Conference (DRC), Univ. of California, Santa Barbara, June 2011 [PDF]
  10. Feng Li, Zhao Fang, Rajiv Misra, Srinivas Tadigadapa, Qiming Zhang,Suman Datta, "Giant magnetoelectric effect in nanofabricated Pb(Zr0.51Ti0.48)O3-Fe85B5Si10 Cantilevers and resonant gate transistors", accepted for publication in Device Research Conference (DRC), Univ. of California, Santa Barbara, June 2011 [PDF]
  11. L. Liu, V. Saripalli, V. Narayanan and S. Datta, "Experimental Investigation of Scalability and Transport in In0.7Ga0.3As Multi-Gate Quantum Well FET (MuQFET)", accepted for publication in Device Research Conference (DRC), Univ. of California, Santa Barbara, June 2011 [PDF]
  12. H. Madan, D. Veksler, Y.T. Chen, J. Huang, N. Goel, G. Bersuker and S. Datta, "Interface States at high-k/InGaAs interface: H2O vs. O3 based ALD Dielectric", accepted for publication in Device Research Conference (DRC), Univ. of California, Santa Barbara, June 2011 [PDF]
  13. C. D. Young, M. Baykan, A. Agrawal, H. Madan, K. Akarvardar, C. Hobbs, I. OK, W. Taylor, C. E. Smith, M. M. Hussain, T. Nishida, S. Thompson, P. Majhi, P. Kirsch, S. Datta and R. Jammy, "Critical Discussion on (100) and (110) Orientation Dependent Transport : nMOS Planar and FinFET", accepted for publication in Intl. Symposium on VLSI Technology (VLSI), Kyoto, Japan, June, 2011. [PDF]
  14. L. Liu, V. Saripalli, E. Hwang, V. Narayanan and S. Datta, "Multi-Gate Modulation Doped In0.7Ga0.3As Quantum Well FET for Ultra Low Power Digital Logic", accepted for publication in 219th Electro chemical Society (ECS) Meeting, Montreal, Canada, May 1-6, 2011. [PDF]
  15. V. Saripalli, A. Misra, S. Datta and V. Narayanan, "An Energy-Efficient Heterogeneous CMP based on Hybrid TFET-CMOS Cores," accepted for publication in Design Automation Conference (DAC), San Diego, June 5-10, 2011. [PDF]
  16. Y.C. Chen, S. Soumya, G. Sun, Y. Xie, S. Datta and V. Narayanan, "Automated Mapping for Reconfigurable Single Electron Transistor Arrays," accepted for publication in Design Automation Conference (DAC) , San Diego, June 5-10, 2011. [PDF]

    17. 2010

    Journals:

  17. A. Vallett, S. Minassian, P. Kaszuba, S. Datta, J. M. Redwing and T.S. Mayer, "Fabrication and Characterization of Axially Doped Silicon Nanowire Tunnel Field-Effect Transistors," NanoLetters, vol. 10, pp. 4813-4818, November 2010. [PDF]
  18. I. Geppert, M. Eizenberg, A. Ali and S. Datta, "Band offsets determination and interfacial chemical properties of the Al2O3/GaSb system," Applied Physics Letters, vol. 97, pp. 162109, October 2010. [PDF]
  19. F. Li, F. Zhao, Q. M. Zhang and S. Datta, "Low-frequency voltage mode sensing of magnetoelectric sensor in package," Electronics Letters, vol. 46, no. 16, pp. August 2010. [PDF]
  20. A. Ali, H. S. Madan, A. P. Kirk, R. M. Wallace, D. A. Zhao, D. A. Mourey, M. K. Hudait, T. N. Jackson, B. R. Bennett, J. B. Boos, and S. Datta, "Fermi Level Unpinning of GaSb (100) using Plasma Enhanced Atomic Layer Deposition of Al2O3 Dielectric," Applied Physics Letters, vol. 97, pp. 143502, October 2010. [PDF]
  21. W.C. Kao, A. Ali, E. Hwang, S. Mookerjea and S. Datta "Effect of interface states on sub-threshold response of III-V MOSFETs, MOS HEMTs and tunnel FETs", Solid-State Electronics, vol.54, pp. 16665-1668, August 2010. [PDF]
  22. V. Saripalli, L. Liu, S. Datta and V. Narayanan, "Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits", Journal of Low Power Electronics, vol. 6, no. 3, pp. October 2010. [PDF]
  23. S. Mookerjea, D. Mohata, T. Mayer, V. Narayanan, S. Datta, "Temperature-Dependent I-V Characteristics of a Vertical In0.53Ga0.47As Tunnel FET," IEEE Electron Device Letters, vol. 31, no. 6, pp. 564-567, June 2010. [PDF]
  24. B. Downey, S. Datta and S. Mohney,"Numerical study of reduced contact resistance via nanoscale topography at metal/semiconductor interfaces," Semiconductor Science and Technology vol. 25, no. 1, pp 1-4, January 2010.[PDF]
  25. A.Ali , H. Madan, S. Koveshnikov, S. Oktyabrsky, R. Kambhampati, T. Heeg, D. Schlom and S. Datta,"Small Signal Response of Inversion Layers in High Mobility In0.53Ga0.47As MOSFETs Made with Thin High-k Dielectrics," IEEE Transactions on Electron Devices vol. 57, no. 4, pp. 742-748, April 2010.[PDF]
  26. F. Li, S. H. Lee, Z. Fang, P. Majhi, Q. Zhang, S. K. Banerjee, and S. Datta, "Flicker Noise Improvement in 100 nm Lg Si0.50Ge0.50 Strained Quantum-Well Transistors using Ultra-Thin Si Cap Layer," IEEE Electron Device Letters, vol. 31, no. 1, pp. 47-49, January 2010.[PDF]

    27. Conferences:

  27. A. Ali, H. Madan, R. Misra, E.Hwang, A. Agrawal, P. Schiffer, J. B. Boos, B. R. Bennett, I. Geppert, M. Eizenberg and S. Datta,"Advanced Composite High-k Gate Stack for Mixed Anion Arsenide-Antimonide Quantum Well Transistors," Accepted in IEEE International Electron Devices Meeting (IEDM 2010).[PDF]
  28. S. Datta, A. Ali, S. Mookerjea, V. Saripalli, L. Liu, S. Eachempati, T. Mayer and V. Narayanan, "Non-silicon logic elements on silicon for extreme voltage scaling," Proceedings of the Silicon Nanoelectronics Workshop (SNW), pp.15-16, Honolulu, Hawaii, June 2010 (Invited Talk)[PDF]
  29. S. Datta, ,"Compound Semiconductor Based Tunnel Transistor Logic," Lester Eastman Conference on High Performance Devices (LEC 2010), pp.178-179, Troy, USA, August 2010 (Invited Talk)[PDF]
  30. A. Ali, H. S. Madan, A. P. Kirk, R.M. Wallace, D. A. Zhao, D. A. Mourey, M. Hudait, T. N. Jackson, B. R. Bennett, J. B. Boos, and S. Datta,"Fermi Level Unpinning of GaSb(100) using Plasma Enhanced ALD Al2O3Dielectric," Device Research Conference Digest(DRC 2010) pp. 27-28, South Bend, Indiana, June 2010.[PDF]
  31. E. Hwang, S. Mookerjea, M. Hudait and S. Datta,"Scalability Study of In0.70Ga0.30As HEMTs for 22nm node and beyond Logic Applications ," Device Research Conference Digest(DRC 2010) pp. 61-62, South Bend, Indiana, June 2010.[PDF]
  32. A. Vallett, S. Minassian, S. Datta, J. Redwing and T. Mayer,"Fabrication of Axially-Doped Silicon Nanowire Tunnel FETs and Characterization of Tunneling Current," Device Research Conference Digest (DRC 2010) pp. 273-274, South Bend, Indiana, June 2010.[PDF]
  33. D. Pawlik, M. Barth, P. Thomas, S. Kurinec, S. Mookerjea, D. Mohata, S. Datta, S. Cohen, D. Ritter, S. Rommel,"Sub-Micron In0.53Ga0.47As Esaki Diodes With Record Current Density of 1MA/cm2," IEEE Device Research Conference Digest(DRC 2010) pp. 163-164, South Bend, Indiana, June 2010.[PDF]
  34. D. K. Mohata, D. Pawlik, L. Liu, S. Mookerjea, V. Saripalli, S. Rommel and S. Datta,"Implications of Record Peak Current Density In0.53Ga0.47As Esaki Tunnel Diode on Tunnel FET Logic Applications," Device Research Conference Digest (DRC 2010) pp. 101-102, South Bend, Indiana, June 2010.[PDF]
  35. L. Liu and S. Datta,"Investigation of the Scalability of Ultra Thin Body Double Gate Tunnel FET using Physics based 2D Analytical Model," IEEE Device Research Conference Digest (DRC 2010), pp. 103-104, South Bend, Indiana, June 2010.[PDF]
  36. V. Saripalli, D. K. Mohata, S. Mookerjea, S. Datta and V. Narayanan,"Low Power Loadless 4T SRAM cell based on Degenerately Doped Source (DDS) In0.53Ga0.47As Tunnel FETs," IEEE Device Research Conference Digest (DRC 2010) pp. 103-104, South Bend, Indiana, June 2010.[PDF]
  37. S. Datta, S. Mookerjea, D. Mohata, L. Liu, V. Saripalli, V. Narayanan and T. Mayer, "Compound Semiconductor Based Tunnel Transistor Logic," IEEE CS MANTECH Conference, pp. 203-204, Portland, Oregon, May 2010 (Invited talk by the candidate). [PDF]
  38. S. Datta, "III-V compound  MOSFET and TFET devices," Proceedings of the IEEE 11th Ultimate Integration of Silicon (ULIS) Conference, Glasgow, Scotland, March 2010 (Plenary Talk by the candidate).[PDF]
  39. J. Singh, R. Krishnan, S. Mookerjea, S. Datta, V. Narayanan,"A Novel Si TFET Based SRAM design for Ultra Low-Power 0.3V VDD Applications," Proceedings of 15th Asia Pacific Design Automation Conference (ASP-DAC 2010), Yokohama, Japan, January 2010.[PDF]
  40. V. Saripalli, V.,S. Datta and N. Vijaykrishnan,"Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors," International Conference on VLSI Design, India pp. 399-404, Bangalore, India, January 2010.[PDF]

    41. 2009

    Journals:

  41. S. Mookerjea, R. Krishnan, S. Datta and V. Narayanan, "On Enhanced Miller Capacitance in Inter-Band Tunnel Transistors," IEEE Electron Device Letters, vol. 30, no. 10, pp. 1102-1104, October 2009.[PDF]
  42. S. Mookerjea, R. Krishnan, S. Datta and V. Narayanan, "Effective Capacitance and Drive Current for Tunnel-FET (TFET) CV/I Estimation,"IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 2092-2098, September 2009 .[PDF]
  43. Z. Fang, S. G. Lu, F. Li, S. Datta and Q. M. Zhang, "Enhancing the Magnetoelectric Response of Metglas/Polyvinylidene fluoride Laminates by Exploiting the Flux Concentration Effect", Applied Physics Letters, 112903, September 2009.[PDF]

    44. Conferences:

  44. S. Mookerjea, D. Mohata, R. Krishnan, J. Singh, A. Vallett, A. Ali, T. Mayer, V. Narayanan, D. Schlom, A. Liu and S. Datta, "Experimental Demonstration of 100nm Channel Length In0.53Ga0.47As-based Vertical Inter-band Tunnel Field Effect Transistors (TFETs) for Ultra Low-Power Logic and SRAM Applications" IEEE International Electron Devices Meeting (IEDM) Technical Digest, pp. 949-951, December, 2009.[PDF]
  45. H. Madan, A.Ali, S. Koveshnikov and S. Datta, "Interface State Response in HfO2 Gated Strained InAs Quantum-well FETs," Accepted in 40th IEEE Semiconductor Interface Specialists Conference (SISC), December 2009.[PDF]
  46. W. C. Kao, E. Hwang, S. Mookerjea and S. Datta, "Impact of Interface States on Sub-threshold Response of III-V MOSFETs, MOS HEMTs and Tunnel FETs", Accepted in 40th IEEE Semiconductor Interface Specialists Conference (SISC), December 2009.[PDF]
  47. A. Ali , H. Madan, S. Koveshnikov, S. Oktyabrsky, R. Kambhampati, T. Heeg, D. Schlom and S. Datta, "Small Signal Response of Inversion Layers in High Mobility In0.53Ga0.47As MOSFETs Made with Thin High-k Dielectrics",ECS Transactions, vol.25, no. 6, pp. 271-284,"Physics and Technology of High-k Gate Dielectrics" October 2009.[PDF]
  48. V. Saripalli, N. Vijaykrishnan and S. Datta, " Ultra Low Energy Binary Decision Diagram Circuits using Few Electron Transistors", Workshop on Nano-Bio Sensing Paradigms and Applications (in conjunction with Nanonet 2009) , October 2009.
  49. Z. Fang, S. Lu, F. Li, N. Mokhariwale, S. Datta and Q.M. Zhang, "Sensitivity enhancement of magnetic sensors based on Metglas/PVDF laminates using the flux concentration effect," Nanoelectronic Devices for Defense and Security Conference (NANO DDS), September 2009.[PDF]
  50. S. Mookerjea and S. Datta, "Band-gap Engineered Hot Carrier Tunnel Transistors," 67th Device Res. Conference (DRC), pp. 121-122, June 2009.[PDF]
  51. A. Ali, S. Mookerjea, E. Hwang, S. Koveshnikov, S. Oktyabrsky, V. Tokranov, M. Yakimov, R. Kambhampati, W. Tsai and S. Datta, "HfO2 Gated, Self Aligned and Directly Contacted Indium Arsenide Quantum-well Transistors for Logic Applications - A Temperature and Bias Dependent Study," 67th Device Research Conference (DRC), pp. 55-56, June 2009.[PDF]
  52. D. J. Pawlik, P. Thomas, M. Barth, K. Johnson, S.L. Rommel, S. Mookerjea , S. Datta, M. Luisier , G. Klimeck, Z.Cheng, J. Li, J.S. Park, J.M. Hydrick, J.G. Fiorenza, and A. Lochtefeld, "Indium Gallium Arsenide on Silicon Interband Tunnel Diodes for NDR-based memory and Steep Subthreshold Slope Transistor Applications," 67th Device Research Conference (DRC), pp. 69-70, June 2009.
  53. S. Mookerjea, R. Krishnan, A. Vallett, T. Mayer and S. Datta, "Inter-band Tunnel Transistor Architecture using Narrow Gap Semiconductors," ECS Transactions, vol. 19, issue 5, pp. 287-292, "Graphene and Emerging Materials for Post-CMOS Applications", May 2009.[PDF]

    54. 2008

    Journals:

  54. D. Schlom, S. Guha and S. Datta, "Gate Oxides Beyond SiO2", MRS Bulletin, pp. 1017-1025, November 2008.
  55. S. H. Lee, P. Majhi, J. Oh, B. Sassman, C. Young, A. Bowonder, W. Y. Loh, J. J. Choi, B. J. Cho, H. D. Lee, P. Kirsch, H. R. Harris, W. Tsai, S. Datta, H. H. Tseng, S. K. Banerjee, and R. Jammy, "Demonstration of Lg 55 nm pMOSFETs With Si/ Si0.25Ge0.75/ Si Channels, High Ion Ioff (5x104), and Controlled Short Channel Effects (SCEs)", IEEE Electron Device Letters, vol 29, No 9, 1017-1020 September 2008.
  56. C. I Kuo, H. T Hsu, E. Y. Chang, C. Y. Chang, Y. Miyamoto, S. Datta, M. Radosavljevic, G. W. Huang and C.T. Lee, "RF and Logic Performance Improvement of In0.7Ga0.3As/InAs/In0.7Ga0.3As Composite-Channel HEMT Using Gate-Sinking Technology", IEEE Electron Device Letters, vol. 29, no. 4, pp. 290-293, April 2008.

    57. Conferences:

  57. N. Goel, D. Heh, S. Koveshnikov, I. OK, S. Oktyabrsky, V. Tokranov, R. Kambhampati, M. Yakimov, Y. Sun, P. Pianetta, C. Gaspe, M. Santos, J. Lee, S. Datta, P. Majhi, and W. Tsai, "Addressing The Gate Stack Challenge For High Mobility InxGa1-xAs Channels For NFETs", International Electron Devices Meeting Technical Digest (IEDM) pp. 363-366, December, 2008.
  58. S. Datta, "Sub-Quarter Volt Supply Voltage III-V Tunnel Transistors for Green Nanoelectronics" 39th IEEE Semiconductor Interface Specialists Conference (SISC), December 2008 (Invited Talk).
  59. V. Saripalli, S. Mookerjea, S. Datta, and V. Narayanan, "Ultra low power signal processing architectures," IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 333 - 336, Nov. 2008.[PDF]
  60. S. Mookerjea and S. Datta, "Comparative Study of Si, Ge and InAs Based Steep Subthreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications," 66th Device Research Conference (DRC), pp. 47-48, Jun. 2008.[PDF]
  61. S. Datta, "Compound Semiconductor as CMOS Channel Material - Deja vu or New Paradigm?" 66th Device Research Conference (DRC), pp 33-36, June 2008 (Invited Talk).
  62. S. Eachempati, V. Saripalli, N. Vijaykrishnan and S. Datta, "Reconfigurable BDD Based Quantum Circuits," IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 61-67, June 2008.
  63. S. Datta, "Enabling Green Transistors with Narrow Bandgap Ccompound Semiconductors", 32nd Workshop on Compound Semiconductor Devices and Integrated Circuits (WOCSDICE), May 2008 (Invited Talk).

    64. 2007

    Journals:

  64. R. Chau, B. Doyle, S. Datta, K. Kavalieros and K. Zhang, "Integrated nanoelectronics for the future", Nature Materials, vol 6, pp. 810-812, November 2007.[PDF]
  65. C. Y. Chang, H. T. Hsu, E. Y. Chang, C. I. Kuo, S. Datta, M. Radosavljevic, M. Miyamoto, G.W. Y. Huang "Investigation of Impact Ionization in InAs-Channel HEMT for High-Speed and Low-Power Applications", IEEE Electron Device Letters, vol. 28, no. 10, pp. 856-858, October 2007.
  66. S. Datta, "III-V field-effect transistors for low power digital logic applications", Journal of Microelectronic Engineering, vol. 84 , no. 9-10, pp. 2133-2137, September 2007.[PDF]
  67. S. Datta, G. Dewey, J. M. Fastenau, M. K. Hudait, D. Loubychev, W. K. Liu, M. Radosavljevic, W. Rachmady and R. Chau, "Ultrahigh-Speed 0.5 V Supply Voltage In0.7Ga0.3As Quantum-Well Transistors on Silicon Substrate", IEEE Electron Device Letters, vol. 28, no. 8, pp. 685-687, August 2007.[PDF]
  68. T. Ashley, L. Buckle, S. Datta, M.T. Emeny, D.G. Hayes, K.P. Hilton, R. Jefferies, T. Martin, T.J. Phillips, D.J. Wallis, P.J. Wilding and R. Chau, "Heterogeneous InSb quantum well transistors on silicon for ultra-high speed, low power logic applications", Electronics Letters, vol. 43 no. 14, July 2007.[PDF]

    69. Conferences:

  69. M. K. Hudait, S. Datta, G. Dewey, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, R. Pillarisetty, M. Radosavljevic and R. Chau, "Heterogeneous Integration of Enhancement Mode In0.7Ga0.3As Quantum Well Transistor on Silicon Substrate using Thin (<2 um) Composite Buffer Architecture for High-Speed and Low-voltage (0.5V) Logic Applications", International Electron Devices Meeting Technical Digest (IEDM), pp. 625-628, December 2007.[PDF]
  70. S. Datta, "Prospects of Ultra-High Mobility Narrow Gap Semiconductor Quantum Wells for Very Low-Power Logic Applications", International Symposium on Advanced Silicon-based Nano-devices (ISASN), Tokyo, Japan, November 2007
  71. M. Chandhok, S. Datta, D. Lionberger, S. Vesecky "Impact of Line Width Roughness of Intel's 65 nm Process Devices", Proceedings of SPIE, pp. 6519, 2007.

    72. 2006

    Journals:

    Conferences:

  72. J. Kavalieros, B. S. Doyle, S. Datta, G. Dewey and R. Chau "Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering," Digest of Technical Papers VLSI Technology Symposium, pp.62-63, June 2006.[PDF]
  73. S. Datta, "Antimonide based Quantum Well Transistors for High Speed, Low Power Logic Applications", Proceedings of the International Conference on Indium Phosphide and Related Materials (IPRM), Princeton, pp. 174 - 176, May 2006.
  74. S. Datta, " Emerging Nano-electronic Devices for High-Speed, Low-Power Applications", IEEE VLSI Test Symposium (VTS), Berkeley, May 2006.

    75. 2005

    Journals:

  75. R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, B. Jin, M. Metz, A. Majumdar and M. Radosavljevic, "Application of high-K gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology," Journal of Microelectronic Engineering, vol. 80, no. 17, pp. 1-6, June 2005.[PDF]
  76. R. Chau, S. Datta, M. Doczy, et al. "Benchmarking nanotechnology for high-performance and low-power logic transistor applications," IEEE Transactions on Nanotechnology, vol. 4, no. 2, pp. 153-158, March 2005.[PDF]

    77. Conferences:

  77. S. Datta, T. Ashley, J. Brask, L. Buckle, M. Doczy, M. Emeny, D. Hayes, K. Hilton, R. Jefferies, T. Martin, T. Phillips, D. Wallis, P. Wilding, R. Chau, "85nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications", International Electron Devices Meeting (IEDM) Technical Digest, pp. 763-766, Dec 2005.[PDF]
  78. R. Chau, S. Datta and A. Majumdar, "Opportunities and Challenges of III-V Nanoelectronics for Future High-speed, Low-power Logic Applications," Technical Digest, IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), pp. 17-20, Nov. 2005.[PDF]
  79. S. Datta, "Silicon and III-V nanoelectronics", Proceedings of the International Conference on Indium Phosphide and Related Materials (IPRM), Glasgow, Scotland, pp. 7 - 8, May 2005
  80. R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, B. Jin, M. Metz, A. Majumdar and M. Radosavljevic, "Emerging Silicon and Non-Silicon Nano-electronic Devices: Opportunities and Challenges for Future High-Performance and Low-Power Computational Applications," Proceedings of Technical Papers, IEEE VLSI-TSA International Symposium on VLSI Technology (VLSI TSA), Hsinchu, Taiwan, pp. 13-16, April 2005.

    81. 2004

    Journals:

  81. R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros and M. Metz, "High-K/Metal-Gate Stack and Its MOSFET Characteristics," IEEE Electron Device Letters, vol. 25, no. 6, pp. 408-410, June 2004.[PDF]

    82. Conferences:

  82. S. Datta, T. Ashley, A. Barnes, L. Buckle, A. Dean, M. Emeny, M. Fearn, D. Hayes, K. Hilton, R. Jefferies, T. Martin, K. Nash, T. Philips, W. Tang, P. Wilding and R. Chau, "Novel InSb-based Quantum Well Transistors for Ultra-High Speed, Low Power Logic Applications," Proceedings 7th International Conference on Solid-State and Integrated Circuits Technology (ICSICT), pp. 2253-2256, Beijing, China, Oct. 2004
  83. S. Datta, "Advanced Si and SiGe Strained NMOS and PMOS Transistors with High-K/Metal-Gate Stack," Proceedings of the Bipolar/BiCMOS Circuits and Technology Meetings (BCTM), Montreal, Canada, pp. 194-197, Sept. 2004.[PDF]
  84. B. Jin, S. Datta, G. Dewey, M. Doczy, B. Doyle, K. Johnson, J. Kavalieros, M. Metz, U. Shah, N. Zelick and R. Chau, "Mobility Enhancement in Compressively Strained SiGe Surface Channel pMOS(FET) with HfO2/TiN Gate Stack," Proceedings of the ECS 2004 Joint International Meeting, SiGe: Materials Processing and Devices, pp. 111-122, Oct. 2004

    85. 2003

    Journals:

  85. B.S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, "High Performance Fully-Depleted Tri-Gate CMOS Transistors," IEEE Electron Device Letters, Vol. 24, No. 4, pp.263-265, April 2003.[PDF]
  86. R. Chau, B. Boyanov, B. Doyle, M. Doczy, S. Datta, S. Hareland, B. Jin, J. Kavalieros, and M. Metz, "Silicon Nano-transistors for Logic Applications," PHYSICA E, Low-Dimensional Systems and Nanostructures, Vol. 19, Issues 1-2, pp.1-5, July 2003.[PDF]

    87. Conferences:

  87. S. Datta, G. Dewey, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, M. Metz, N. Zelick and R. Chau, "High mobility Si/SiGe strained channel MOS transistors with HfO2/TiN gate stacks", International Electron Devices Meeting (IEDM) Technical Digest, pp. 28.1.1 - 28.1.4, December 2003. [PDF]
  88. R. Chau, S. Datta, M. Doczy, J. Kavalieros and M. Metz, "Gate Dielectric Scaling for High-Performance CMOS: from SiO2 to High-K," Extended Abstracts of International Workshop on Gate Insulator (IWGI), Tokyo, Japan, pp.124-126, Nov. 2003.
  89. R. Chau, B. Doyle, M. Doczy, S. Datta, S. Hareland, B. Jin, J. Kavalieros and M. Metz, "Silicon Nano-Transistors and Breaking the 10nm Physical Gate Length Barrier," 61st Device Research Conference (DRC), pp.123-126, June 2003. [PDF]

    90. 2002

    Journals:

    Conferences:

  90. R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Murthy, M. Doczy, R. Arghavani, and S. Datta, "Advanced Depleted-Substrate Transistors: Single-gate, Double-Gate and Tri-gate," Extended Abstracts of the International Conference on Solid-State Devices and Materials (SSDM), pp. 68-69, 2002.

    91. 2000

    Journals:

  91. S. Datta, K. P. Roenker, M. M. Cahay and L. M. Lunardi , " Analytical Modeling of Pnp InP/InGaAs Heterojunction Bipolar Transistors," Solid State Electronics , vol. 44, no. 7, pp. 1331-1333, July 2000 .
  92. S. Datta, K. P. Roenker and M. M. Cahay, "A Gummel-Poon Model for Pnp Heterojunction Bipolar Transistors with a Compositionally Graded Base," Solid-State Electronics, vol. 44, no. 6, pp. 991-1000, June 2000.

    93. Conferences:

  93. S. Datta, K. P. Roenker, R. E. Peddenpohl II and M. M. Cahay, "Analysis of High Current Effects on the Performance of Pnp InP-Based Heterojunction Bipolar Transistors," Proceedings of Twelfth International Conference on InP and Related Materials (IPRM), pp. 134-137, May 2000.

    94. 1999

    Journals:

  94. S. Datta, K. P. Roenker and M. M. Cahay , " Emitter Series Resistance Effect of Multiple Heterojunction Contacts for Pnp Heterojunction Bipolar Transistors," Solid-State Electronics , vol. 43, no. 7, pp. 1299-1305, 1999 .
  95. S. Datta, K. P. Roenker and M. M. Cahay , " Hole Transport and Quasi-Fermi Level Splitting at the Emitter-Base Junction in Pnp Heterojunction Bipolar Transistors," Journal of Applied Physics , vol. 85, no. 3, pp. 1949-1955, Feb 1999 .
  96. S. Datta, K. P. Roenker and M. M. Cahay , " Implications of Hole versus Electron Transport Properties for High Speed Pnp Heterojunction Bipolar Transistors," Solid-State Electronics , vol. 43, no. 1, pp. 73-80, Jan 1999 .

    97. Conferences:

  97. S. Datta, K. P. Roenker, and M. M. Cahay , " Base Pushout and High Current Effects in InP-Based Pnp Heterojunction Bipolar Transistors," Proceedings of the State-of-the-Art Program on Compound Semiconductors , Electrochemical Society, vol.99-17, Oct. 1999 .

    98. 1998

    Journals:

  98. S. Datta, S. Shi, K. P. Roenker and M. M. Cahay and W. E. Stanchina , " Simulation and Design of InAlAs/InGaAs Pnp Heterojunction Bipolar Transistors ," IEEE Transactions on Electron Devices , vol. 45, no. 8, pp. 1634-1643, Aug. 1998 .
  99. S. Datta, K. P. Roenker and M. M. Cahay , " A Thermionic-Emission-Diffusion Model for a Graded Base Pnp Heterojunction Bipolar Transistors," Journal of Applied Physics , vol. 83, no. 12, pp. 8036-8045, June 1998 .

    100. Conferences:

  100. S. Datta, K. P. Roenker and M. M. Cahay , " High Current and Two Dimensional Effects in InP-Based Pnp Heterojunction Bipolar Transistors ," Proceedings of the State-of-the-Art Program on Compound Semiconductors , , Electrochemical Society, vol. 98-12, 1998 .

    101. 1997

    Journals:

    Conferences:

  101. S. Datta, S. Shi, K. P. Roenker and M. M. Cahay , " Base Design for Pnp InAlAs/InGaAs Heterojunction Bipolar Transistors ," Proceedings of the State-of-the-Art Program on Compound Semiconductors, Electrochemical Society , vol. 97-1, pp. 272-287, 1997 .
  102. S. Datta, S. Shi, K. P. Roenker, M. M. Cahay and W. E. Stanchina , " Numerical Modeling and Design of Pnp InAlAs-InGaAs Heterojunction Bipolar Transistors ," Proceedings of the Ninth International Conference on InP and Related Materials (IPRM) , pp. 392-395, 1997 .