2009 Presentations
Jitter
Technical Papers
By Ransom Stephens, Writer, Physicist, Public Speaker
Techniques for jitter analysis exploded on the scene several years ago with the introduction of Total Jitter defined at a Bit Error Ratio, TJ(BER). This presentation is an in-depth review of jitter and its analysis from the definition of TJ(BER) to the dual-Dirac model, analysis techniques from phase noise analysis to the alphabet soup – RJ, DJ, PJ, SJ, ISI, DDJ, BUJ, etc. – and design methods that minimize the impact of jitter on the Bit Error Ratio through, for example, the use of clock/data recovery at the receiver. Please bring your questions, concerns, moments of doubt, wisecracks and prejudices – with this breadth of material, Ransom would rather focus on what’s bothering you right now than the slides he assembled on the plane.
USB 3.0 Electrical Challenges and Solutions
By Howard Heck, Principal Engineer, Intel Corporation
The 10x performance increase provided by USB 3.0 creates multiple challenges for system and circuit designers. The increased bandwidth of the signals brings with it proportional increases in loss and crosstalk, significantly reducing voltage margins. This demands improved cable designs and the implementation of equalization techniques. Smaller data bit widths shrink timing margins, requiring improved PLL and clock recovery designs and more accurate testing techniques. In this talk, we provide insight into the nature and severity of the challenges, discuss the implications for I/O and interconnect channel designs, and present specifications and design techniques that will make the performance improvements promised by 5 Gb/s SuperSpeed USB a reality in the near future.
GEMS: A General-purpose Electromagnetic Solver for EMI/EMC Problems Arising in Electronic Packages
By Raj Mittra, Professor, and Neng-Tien Huang, Research Assistant, EMC Lab, Penn State University; Gary Biddle, Engineer, Foxconn Corporation
Practicing engineers engaged in the design of electronic packages are embracing the increasingly popular trend of simulating first, and then following through with the fabrication of only those configurations that show excellent promise during this step. The success of this paradigm rests squarely on the availability of reliable CAD tools, which can handle complex electromagnetic systems in a time-efficient manner, without making gross approximations that are often employed in an attempt to make the problem “manageable,” which it would not otherwise be, because of the heavy demands it would place on the available computer facilities.
This talk will introduce a general-purpose EM solver (GEMS), which has been developed for the purpose of modeling SI characteristics of multilayer boards, connectors and electronic packages, in general. In addition, it is useful for characterizing mode-stir chambers often used for EMI/EMC measurements. A wide variety of applications of GEMS to various real-world problems will be described. A parallelized version of the code, which enables us to solve problems involving 10E+9 (10 billion) or more unknowns, 4 orders of magnitude larger than is possible with existing commercially available codes, with only a very moderate investment in cost, will be discussed. Other practical aspects of using GEMS, namely importing the geometry of the object to be simulated into the code from an engineering CAD file, also will be covered.
Via and Via Array Modeling on Crosstalk
By Jun Fan, Assistant Professor, Missouri University of Science and Technology
Crosstalk among vias is a critical problem in high-speed digital circuits, deteriorating signal quality and increasing jitter, especially when circuit density is high. Underlying mechanism of crosstalk among vias is investigated in this paper. Using a physics-based equivalent circuit model, crosstalk as a function of various geometrical parameters, including parallel plane pair thickness, layer count in printed circuit board (PCB) stackup, ground via patterns, and parallel plane pair dimensions, has been investigated. A multi-step crosstalk evaluation procedure is proposed based on the study for PCB layout-design verifications.
Improved De-Embedding Techniques for Highly-Coupled Multiport Fixtures
By Jon Martens, Engineer, Anritsu Company
General de-embedding techniques for highly-coupled fixtures can be quite complicated since the number of required standards (dummy structures) rises very rapidly with port count. In addition, the required accuracy of knowledge of these standards increases with the degree of coupling, and in some cases, with port count as well. Some simplifying assumptions about the reciprocity of the fixture and the relative path losses (direct vs. coupled) can reduce the number of standards and the knowledge requirements while still maintaining more generality than a fixture-specific circuit model. Some examples will be presented showing the standards reduction as well as an assessment of the effect of standards errors on resultant measurement accuracy.
